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| 1. general description the tda8034hn is a cost-effective analog interface for asynchronous and synchronous smart cards operating at 5 v, 3 v or 1.8 v. using few external components, the tda8034hn provides all supply, protection and control functions between a smart card and the microcontroller. 2. features and benefits ? integrated circuit smart card interface in an hvqfn24 package ? 5v, 3v or 1.8v smart card supply ? very low power consumption in deep shutdown mode ? three protected half-duplex bidirectional buffered i/o lines (c4, c7 and c8) ? v cc regulation: ? 5v, 3v or 1.8v 5 % using two low esr multilaye r ceramic capacitors: one of 220 nf and one of 470 nf ? current spikes of 40 na/s (v cc = 5 v and 3 v) or 15 na/s (v cc =1.8 v) up to 20 mhz, with controlled rise and fall ti mes and filtered overload detection of approximately 120 ma ? thermal and short-circuit protection for all card contacts ? automatic activation and deactivation sequences triggered by a short-circuit, card take-off, overheating, falling v dd , v dd(intf) or v ddp ? enhanced card-side electrostatic discharge (esd) protection of > 6 kv ? external clock input up to 26 mhz connected to pin xtal1 ? card clock generation up to 20 mhz using pins clkdiv1 and clkdiv2 with synchronous frequency changes of f xtal , 1 2 f xtal, 1 4 f xtal or 1 8 f xtal ? non-inverted control of pin rst using pin rstin ? compatible with iso 7816, nds and emv 4.2 payment systems ? supply supervisor for killing spik es during power on and off: ? using a fixed threshold ? using an external resistor bridge with threshold adjustment ? built-in debouncing on card presence contacts (typically 8 ms) ? multiplexed status signal using pin offn tda8034hn smart card interface rev. 2.0 ? 12 november 2010 product data sheet
tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 2 of 30 nxp semiconductors tda8034hn smart card interface 3. applications ? pay tv ? electronic payment ? identification ? bank card readers 4. quick reference data [1] to meet these specifications, v cc should be decoupled to pin gnd using two ceramic mult ilayer capacitors of low esr with values of either 100 nf or one 220 nf and one 470 nf. table 1. quick reference data v ddp =5v; v dd =3.3v; v dd(intf) =3.3v; f xtal =10mhz; gnd=0v; t amb = 25 c; unless otherwise specified. symbol parameter conditions min typ max unit supply v ddp power supply voltage pin v ddp ; regulator input v cc = 5 v 4.85 5 5.5 v v cc = 3 v and 1.8 v 3 3.3 5.5 v v dd supply voltage pin v dd 2.7 3.3 3.6 v v dd(intf) interface supply voltage pin v dd(intf) 1.6 3.3 v dd +0.3 v i dd supply current shutdown mode - - 35 a deep shutdown mode - - 12 a i ddp power supply current shutdown mode; f xtal stopped - - 5 a active mode; f clk = 1 2 f xtal ; no load --1.5ma i dd(intf) interface supply current shutdown mode - - 6 a card supply voltage: pin v cc [1] v cc supply voltage active mode; i cc <65ma dc 5 v card 4.75 5.0 5.25 v 3 v card 2.85 3.05 3.15 v 1.8 v card 1.71 1.83 1.89 v active mode; current pulses of 40 na/s at i cc <200ma; t < 400 ns 5 v card 4.65 5.0 5.25 v 3 v card 2.76 - 3.20 v active mode; current pulses of 15 na/s at i cc < 200 ma, t < 400 ns; 1.8 v card 1.66 - 1.94 v v ripple(p-p) peak-to-peak ripple voltage from 20 khz to 200 mhz - - 350 mv i cc supply current v cc =0v to 5v, 3v or 1.8v - - 65 ma general t deact deactivation time see figure 8 on page 11 35 90 250 s p tot total power dissipation t amb = ? 25 cto+85 c --0.25w t amb ambient temperature ? 25 - +85 c tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 3 of 30 nxp semiconductors tda8034hn smart card interface 5. ordering information 6. block diagram table 2. ordering information type number package name description version tda8034hn hvqfn24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 4 0.85 mm sot616-1 alarmn, clkup, en1, pvcc, en4, en3, en2 and clk are internal signals. (1) optional external resistor bridge, if not required connect pin poradj to ground. fig 1. block diagram 001aal136 100 nf 100 nf 100 nf 470 nf 220 nf 10 f internal oscillator thermal protection crystal oscillator reset generator v cc ldo clock generator i/o transceiver i/o transceiver i/o transceiver clock circuit level shifter c5 card connector c1 c6 c2 c7 c3 c8 c4 sequencer supply internal reference voltage sense 12 gnd en1 alarmn presn 8 poradj 18 rstin 3 cmdvccn 5 offn 19 clkdiv1 6 clkdiv2 7 vcc_sel2 2 vcc_sel1 4 i/ouc 20 21 22 clkup en4 124 23 xtal2 aux2uc aux1uc xtal1 v dd(intf) en3 en2 clk pvcc i/o 9 clk 13 rst 14 v cc 15 aux1 10 aux2 11 17 v dd 16 v ddp r2 r1 v dd(intf) (1) tda8034hn tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 4 of 30 nxp semiconductors tda8034hn smart card interface 7. pinning information 7.1 pinning 7.2 pin description fig 2. pin configuration 001aal137 tda8034hn transparent top view clk cmdvccn clkdiv1 rst vcc_sel1 v cc rstin v ddp vcc_sel2 v dd v dd(intf) poradj clkdiv2 presn i/o aux1 aux2 gnd xtal2 xtal1 aux2uc aux1uc i/ouc offn terminal 1 index area 6 13 5 14 4 15 3 16 2 17 1 18 7 8 9 10 11 12 24 23 22 21 20 19 table 3. pin description symbol pin supply type [1] description v dd(intf) 1v dd(intf) p interface supply voltage vcc_sel2 2 v dd(intf) i5v or 3v v cc voltage selection control signal: active low: v cc = 3 v when pin vcc_sel1 is high active high: v cc = 5 v rstin 3 v dd(intf) i microcontroller card reset input; active high vcc_sel1 4 v dd(intf) i 1.8 v v cc voltage selection control signal: active low: v cc = 1.8 v active high: disables 1.8 v selection cmdvccn 5 v dd(intf) i microcontroller start activation sequence input; active low clkdiv1 6 v dd(intf) i sets the clock frequency on pin clk in association with pin clkdiv2; see ta b l e 4 clkdiv2 7 v dd(intf) i sets the clock frequency on pin clk in association with pin clkdiv1; see ta b l e 4 presn 8 v dd(intf) i card presence contact input; active low [2] i/o 9 v cc i/o card input/output data line (c7) [3] aux1 10 v cc i/o auxiliary card input/output data line (c4) [3] aux2 11 v cc i/o auxiliary card input/output data line (c8) [3] gnd 12 - g ground clk 13 v cc o card clock (c3) rst 14 v cc o card reset (c2) v cc 15 v cc p card supply (c1); decouple to pin gnd using one 470 nf capacitor close to pin v cc and one 220 nf capacitor close to card socket contact c1 with an esr < 100 m tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 5 of 30 nxp semiconductors tda8034hn smart card interface [1] i = input, o = output, i/o = input/output, g = ground and p = power supply. [2] if pin presn is high, the card is considered to be presen t. during card insertion, debounci ng can occur on these signals. to counter this, the tda8034hn has a built-i n debouncing timer (typically 8 ms). [3] uses an internal 11 k pull-up resistor connected to pin v cc . [4] uses an internal 20 k pull-up resistor connected to pin v dd(intf) . [5] uses an internal 10k pull-up resistor connected to pin v dd(intf) 8. functional description remark: throughout this document the iso 7816 terminology conventions have been adhered to and it is a ssumed that the reader is familiar with these. 8.1 power supplies the power supply voltage ranges are as follows: ? v ddp : 4.85 v to 5.5 v when vcc_sel2 is high (v cc = 5 v) ? v ddp : 3 v to 5.5 v when vcc_sel2 is low (v cc = 3 v) or when vcc_sel1 is low (v cc = 1.8 v) ? v dd : 2.7 v to 3.6 v all interface signals to the system controller are referenced to v dd(intf) . all card contacts remain inactive during power up or power dow n. after powering up the device, pin offn remains low until pin cmdvccn is set high and pin presn is low. during power down, pin offn goes low when v ddp falls below the falling threshold voltage (v th ). the internal oscillator frequency (f osc(int) ) is only used during the activation sequences. when the card is not activated (pin cmdvccn is high), the internal oscillator is in low frequency mode to reduce power consumption. this device has a low drop-off (ldo) voltage regulator connected to pin v cc , and is used instead of a dc-to-dc converter. it ensures a minimum v cc of 4.75 v and that the power supply voltage on pin v ddp does not fall below 4.85 v when pin vcc_sel2 is high, for a maximum load current of 65 ma. v ddp 16 v ddp p low-dropout regulator input supply voltage v dd 17 v dd p digital supply voltage poradj 18 v dd(intf) i power-on reset threshold adjustment input using an optional external resistor bridge offn 19 v dd(intf) o nmos interrupt to microcontroller [4] ; active low; see section 8.10 on page 11 i/ouc 20 v dd(intf) i/o microcontroller input/output data line [5] aux1uc 21 v dd(intf) i/o auxiliary microcontroller input/output data line [5] aux2uc 22 v dd(intf) i/o auxiliary microcontroller input/output data line [5] xtal1 23 v dd i crystal connection input xtal2 24 v dd o crystal connection output table 3. pin description ?continued symbol pin supply type [1] description tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 6 of 30 nxp semiconductors tda8034hn smart card interface 8.2 voltage supervisor the voltage supervisor monitors the voltage of the v ddp , v dd and v dd(intf) supplies providing both power-on reset (por) and supply drop-out detection during a card session. the supervisor threshold voltages for v ddp and v dd are set internally, and for v dd(intf) externally by pin poradj. as long as v dd is less than v th + v hys , the ic remains inactive irrespective of the command line levels. after v dd has reached a level higher than v th + v hys , the ic remains inactive for the duration of t w . the output of the supervisor is sent to a digital controller in order to rese t the tda8034hn. this defined reset pulse of approximately 8 ms, i.e. (t w = 1024 1 fosc(int)low ), is used internally to maintain the ic in the shutdown mode during the supply voltage power on; see figure 4 . a deactivation sequence is performed when either v dd , v ddp or v dd(intf) falls below v th . remark: f osc(int)low is the low frequency (or inactive) mode of the defined f osc(int) parameter. fig 3. voltage supervisor circuit fig 4. voltage supervisor waveforms 001aal13 8 reference voltage v dd v dd poradj vcc_sel2 v ddp v dd(intf) r1 r2 001aak99 3 t w t w power on supply dropout power off v th + v hys v th v dd alarmn (internal signal) tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 7 of 30 nxp semiconductors tda8034hn smart card interface 8.3 clock circuits the clock signal from pin clk to the card is either supplied by an external clock signal connected to pin xtal1 or generated using a crystal connected between pins xtal1 and xtal2. the tda8034hn automatically detects if an external clock is connected to xtal1, eliminating the need for a separate pin to select the clock source. automatic clock source detection is performed on each activation command (falling edge of the signal on pin cmdvccn). the presence of an external clock on pin xtal1 is checked during a time window defin ed by the internal oscillator. if a clock is detected, the internal crystal oscillator is st opped. if a clock is not detected, the internal crystal oscillator is started. when an external clock is used, it is mandatory that the clock is applied to pin xtal1 before the falling edge of the signal on pin cmdvccn. the clock frequency is selected using pins clkdiv1 and clkdiv1 to be either f xtal , 1 2 f xtal or 1 4 f xtal or 1 8 f xtal as shown in ta b l e 4 . remark: the levels on both pins must not be allowed to change simultaneously but should be separated by a minimum of 10 ns. the frequency change is synchronous and as such during transition, no pulse is shorter than 45 % of the smallest period. in addition, only the first and last clock pulse around the change has the correct width. when dynamically changing the frequency, the modification is only effective after 10 clock periods on pin xtal1. the duty cycle of f xtal on pin clk should be between 45 % and 55 %. if an external clock is connected to pin xtal1, its duty cycle must be between 48 % and 52 %. when the frequency of the clock signal on pin clk is either f xtal , 1 2 f xtal , 1 4 f xtal or 1 8 f xtal , the frequency dividers guarantee a duty cycle between 45 % and 55 %. enclkin and clkxtal are internal signal names. fig 5. basic layout for using an external clock table 4. clock configuration pin clkdiv1 level pin clkdiv2 level pin clk frequency low low 1 8 f xtal low high 1 4 f xtal high high 1 2 f xtal high low f xtal 001aak99 2 digital multiplexer crystal xtal1 xtal2 clkxtal enclkin tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 8 of 30 nxp semiconductors tda8034hn smart card interface 8.4 input and output circuits when pins i/o and i/ouc are pulled high using an 11 k resistor between pins i/o and v cc and/or between pins i/ouc and v dd(intf) , both lines enter the idle state. pin i/o is referenced to v cc and pin i/ouc to v dd(intf) , thus allowing operation at v cc v dd(intf) . the first side on which a fallin g edge occurs becomes the ma ster. an anti-latch circuit disables falling edge detection on the other line, making it th e slave. after a time delay t d , the logic 0 present on the master-side is sent to the slave-side. when the master-side returns logic 1, the slave-side sends logic 1 during time delay (t w(pu) ). after this sequence, both master and slave sides return to their idle states. the active pull-up feature ensures fast lo w-to-high transitions making the tda8034hn capable of delivering more than 1 ma, up to an output voltage of 0.9v cc , at a load of 80 pf. at the end of the active pull-up pulse , the output voltage is dependent on the internal pull-up resistor value and load current. the current sent to and received from the card?s i/o lines is limited to 15 ma at a maximum frequency of 1 mhz. 8.5 shutdown mode after a power-on reset, if pin cmdvccn is hi gh, the circuit enters the shutdown mode, ensuring only the minimum number of circuits are active while the tda8034hn waits for the microcontroller to start a session. ? all card contacts are inactive. the impedance between the contacts and gnd is approximately 200 . ? pins i/ouc, aux1uc and aux2uc are high-impedance using the 11 k pull-up resistor connected to v dd(intf) ? the voltage generators are stopped ? the voltage supervisor is active ? the internal oscillator runs at its lowest frequency (f osc(int)low ) 8.6 deep shutdown mode when the smart card reader is inactive, the tda8034hn will enter deep shutdown mode if pin cmdvccn is forced high and pins vcc_sel1 and vcc_sel2 are low. in deep shutdown mode, all circuits are disabled and pin offn follows the status of pin presn. changing the status of either pin cmdvccn, vcc_sel1 or vcc_sel2 exits deep shutdown mode; see figure 6 . tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 9 of 30 nxp semiconductors tda8034hn smart card interface 8.7 activation sequence the following device activation sequence is app lied when using an external clock; see figure 7 : 1. pin cmdvccn is pulled low (t0). 2. the internal oscillato r is triggered (t0). 3. the internal oscillator chan ges to high fr equency (t1). 4. v cc rises from either 0 v to 3 v or 0 v to 5 v on a controlled slope (t2). 5. pins i/ouc, aux1uc and aux2uc are driven high (t3). 6. the clock on pin clk is applied to the c3 contact (t4). 7. pin rst is enabled (t5). calculation of the time delays is as follows: ? t1 = t0 + 384 1 fosc(int)low ? t2 = t1 ? t3 = t1 + 17t / 2 ? t4 = driven by host controller; > t3 and < t5 ? t5 = t1 + 23t / 2 remark: the value of period t is 64 times the period interval of the internal oscillator at high frequency ( 1 fosc(int)high ); t3 is called t d(start) and t5 is called t d(end) . fig 6. shutdown and deep shutdown mode activation/deactivation 001aal13 9 shutdown cmdvccn vcc_sel1 vcc_sel2 mode (internal pin) offn presn v cc shutdown deactivation sequence shutdown debounce deep shutdown activation activation tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 10 of 30 nxp semiconductors tda8034hn smart card interface 8.8 deactivation sequence when a session ends, the microcontroller sets pin cmdvccn high. the tda8034hn then executes an automatic dea ctivation sequence by counting the sequencer back to the inactive state (see figure 8 ) as follows: 1. pin rst is pulled low (t11). 2. the clock is stopped, pin clk is low (t12). 3. pins i/ouc, aux1uc and aux2uc are pulled low (t13). 4. v cc falls to 0 v (t14). the deactivation sequence is completed when v cc reaches its inactive state. 5. v cc < 0.4 v (t deac ) 6. all card contacts become low-impedance to gnd. however, pins i/ouc, aux1uc and aux2uc remain pulled up to v dd using the 11 k resistor. 7. the internal oscillator return s to its low frequency mode. calculation of the time delays is as follows: ? t11 = t10 + 3t / 64 ? t12 = t11 + t / 2 ? t13 = t11 + t ? t14 = t11 + 3t / 2 ? t deac = t11 + 3t / 2 + v cc fall time oscint = internal oscillator. fig 7. activation sequence at t3 001aal14 0 cmdvccn xtal1 v cc i/o at r clk > 200 ns rstin rst i/ouc oscint t0 t d(end) = t act t1 = t2 t d(start) t4 low frequency high frequency tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 11 of 30 nxp semiconductors tda8034hn smart card interface remark: the value of period t is 64 times the peri od interval of the internal oscillator (i.e. 25 s). 8.9 v cc regulator the v cc buffer is able to continuously deliver up to 65 ma at v cc = 5v, 3v, or 1.8v. the v cc buffer has an internal overload protec tion with a threshold value of approximately 120 ma. this detection is internally filter ed, enabling spurious current pulses up to 200 ma with a duration of a few milliseconds to be drawn by the card without causing deactivation. however, the average curren t value must stay below maximum; see table 8 . 8.10 fault detection the following conditions are monitored by the fault detection circuit: ? short-circuit or high current on pin v cc ? card removal duri ng transaction ? v ddp falling ? v dd falling ? v dd(intf) falling ? overheating fault detection monitors two different situations: ? outside card sessions, pin cmdvccn is high: pin offn is low if the card is not in the reader and high if the card is in the reader. any voltage drop on v dd is detected by the voltage supervisor. this generates an internal power-on reset pulse but does not act upon the pin offn signal. the card is not powered-up and short-circuits or overheating are not detected. oscint = internal oscillator. fig 8. deactivation sequence 001aak9 95 rst clk i/o v cc xtal1 oscint cmdvcc high frequency t10 t11 t12 t13 t deact t14 low frequency tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 12 of 30 nxp semiconductors tda8034hn smart card interface ? in card sessions, pin cmdvccn is low: when pin offn goes low, the fault detection circuit triggers the automatic emergency deactivation sequence (see figure 9 ). when the microcontroller resets pin cmdvccn to high, after the deactivation sequence, pin offn is rechecke d. if the card is still present, pin offn returns to high. this check id entifies the fault as either a hardware problem or a card removal incident. on card insertion or removal, bouncing can occur in the presn signal. this depends on the type of card presence switch in the connector (normally open or normally closed) and the mechanical characteristics of the switch. to correct for this, a debouncing feature is integrated in to the tda8034hn. this feat ure operates at a typical duration of 8 ms (t deb =640 ( 1 fosc(int)low ). figure 10 on page 13 shows the operation of the debouncing feature. on card insertion, pin offn goes high af ter the debounce time has elapsed. when the card is extracted, the automatic card deac tivation sequence is performed on the first high/low transition on pin presn. after this, pin offn goes low. fig 9. emergency deactivation sequence after card removal 001aal14 1 offn presn clk i/o v cc xtal1 oscint t10 t12 t deact t13 t14 rst low frequency high frequency tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 13 of 30 nxp semiconductors tda8034hn smart card interface 9. limiting values remark: all card contacts are protected agains t any short-circuit to any other card contact. stress beyond th e levels indicated in table 5 can cause permanent damage to the device. this is a short-term stress rating only and under no circumstances implies functional operation under long-term stress conditions. (1) deactivation caused by card withdrawal. (2) deactivation caus ed by short-circuit. fig 10. operation of debounce feature with pins offn, cmdvccn, presn and v cc 001aal41 1 presn offn t deb t deb cmdvccn v cc (1) (2) table 5. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v ddp power supply voltage pin v ddp ? 0.3 +6 v v dd supply voltage pin v dd ? 0.3 +4.6 v v dd(intf) interface supply voltage pin v dd(intf) ? 0.3 +4.6 v v i input voltage pins cmdvccn, clkdiv1, clkdiv2, vcc_sel1, vcc_sel2, rstin, offn, poradj, xtal1, xtal2, i/ouc, aux1uc, aux1uc ? 0.3 +4.6 v card contact pins presn, i/o, rst, aux1, aux2 and clk ? 0.3 +6 v t stg storage temperature ? 55 +150 c p tot total power dissipation t amb = ? 25 c to +85 c - 0.25 w t j junction temperature - +125 c t amb ambient temperature ? 25 +85 c v esd electrostatic discharge voltage human body model (hbm) on card pins i/o, rst, v cc , aux1, aux2, clk, presn; within typical application ? 6+6kv human body model (hbm); all other pins ? 2+2kv machine model (mm); all pins ? 200 +200 v field charged device model (fcdm); all pins ? 500 +500 v tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 14 of 30 nxp semiconductors tda8034hn smart card interface 10. thermal characteristics 11. characteristics table 6. thermal characteristics symbol package name parameter conditions typ unit r th(j-a) hvqfn24 thermal resistance from junction to ambient in free air 53 k/w table 7. characteristics of ic supply voltage v ddp = 5 v; v dd = 3.3 v; v dd(intf) = 3.3 v; f xtal = 10 mhz; gnd = 0 v; t amb = 25 c; unless otherwise specified. symbol parameter conditions min typ max unit supply v ddp power supply voltage pin v ddp v cc = 5 v 4.85 5 5.5 v v cc = 3v or 1.8v 3 3.3 5.5 v v dd supply voltage pin v dd 2.7 3.3 3.6 v v dd(intf) interface supply voltage pin v dd(intf) 1.6 3.3 v dd +0.3 v i dd supply current shutdown mode - - 35 a deep shutdown mode - - 12 a i ddp power supply current shutdown mode f xtal stopped - - 5 a active mode f clk = 1 2 f xtal ; no load - - 1.5 ma f clk = 1 2 f xtal ; i cc =65ma -- 70ma i dd(intf) interface supply current shutdown mode - - 6 a v th threshold voltage no external resistors on pin poradj pin v dd falling 2.30 2.40 2.50 v pin v ddp falling; v cc =5v 3.00 4.10 4.40 v external resistors on pin poradj 1.20 1.24 1.29 v v hys hysteresis voltage no external resistors on pin poradj pin v dd 50 100 150 mv pin v ddp ; v cc = 5 v 100 200 350 mv t w pulse width 5.1 8 10.2 ms i l leakage current pin poradj < 0.5 v ? 0.1 +4 +10 a pin poradj > 1 v ? 1- +1 a card supply voltage: pin v cc [1] c dec decoupling capacitance connected to v cc [2] 550 - 830 nf v o output voltage shutdown mode no load ? 0.1 - +0.1 v i o =1ma ? 0.1 - +0.3 v tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 15 of 30 nxp semiconductors tda8034hn smart card interface i o output current shutdown mode; pin v cc connected to ground -- ? 1ma v cc supply voltage active mode; i cc <65ma dc 5 v card 4.75 5.0 5.25 v 3 v card 2.85 3.05 3.15 v 1.8 v card 1.71 1.83 1.89 v active mode; current pulses of 40 na/s at i cc < 200 ma; t < 400 ns 5 v card 4.65 5.0 5.25 v 3 v card 2.76 - 3.20 v active mode; current pulses of 15 na/s at i cc < 200 ma, t < 400 ns;1.8 v card 1.66 - 1.94 v v ripple(p-p) peak-to-peak ripple voltage 20 khz to 200 mhz - - 350 mv i cc supply current v cc = 0 v to 5 v, 3 v or 1.8 v -- 65ma v cc shorted to ground 90 120 150 ma sr slew rate 5 v card 0.055 0.18 0.3 v/ s 3 v card 0.040 0.18 0.3 v/ s 1.8 v card 0.025 0.18 0.3 v/ s crystal oscillator: pins xtal1 and xtal2 c ext external capacitance pins xtal1 and xtal2 (depending on the crystal or resonator specification) - - 15 pf f xtal crystal frequency card clock reference; crystal oscillator 2- 26 mhz f ext external frequency external clock on pin xtal1 0 - 26 mhz v il low-level input voltage crystal oscillator ? 0.3 - +0.3v dd v external clock ? 0.3 - +0.3v dd(intf) v v ih high-level input voltage crystal oscillator 0.7v dd -v dd + 0.3 v external clock 0.7v dd(intf) -v dd(intf) + 0.3 v data lines: pins i/o, i/ouc, aux1, aux2, auxiuc and aux2uc t d delay time falling edge on pins i/o and i/ouc or vise versa -- 200ns t w(pu) pull-up pulse width 200 - 400 ns f io input/output frequency on data lines - - 1 mhz c i input capacitance on data lines - - 10 pf table 7. characteristics of ic supply voltage ?continued v ddp = 5 v; v dd = 3.3 v; v dd(intf) = 3.3 v; f xtal = 10 mhz; gnd = 0 v; t amb = 25 c; unless otherwise specified. symbol parameter conditions min typ max unit tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 16 of 30 nxp semiconductors tda8034hn smart card interface data lines to the card: pins i/o, aux1and aux2 [3] v o output voltage shutdown mode no load 0 - 0.1 v i o =1ma 0 - 0.3 v i o output current shutdown mode; pin i/o grounded -- ? 1ma v ol low-level output voltage i ol =1ma 0 - 0.3 v i ol 15 ma v cc ? 0.4 - v cc v v oh high-level output voltage no dc load 0.9v cc -v cc +0.1 v i oh < ? 40 a; 5 v or 3 v 0.75v cc -v cc +0.1 v i oh < ? 20 a; 1.8 v 0.75v cc -v cc +0.1 v i oh ? 15 ma 0 - 0.4 v v il low-level input voltage ? 0.3 - +0.8 v v ih high-level input voltage v cc = 5 v 0.6v cc -v cc + 0.3 v v cc = 3 v or 1.8 v 0.7v cc -v cc + 0.3 v v hys hysteresis voltage pin i/o - 50 - mv i il low-level input current pin i/o; v il = 0 v - - 600 a i ih high-level input current pin i/o; v ih =v cc -- 10 a t r(i) input rise time v il maximum to v ih minimum -- 1.2 s t r(o) output rise time c l 80 pf; 10 % to 90 %; 0 v to v cc -- 0.1 s t f(i) input fall time v il maximum to v ih minimum -- 1.2 s t f(o) output fall time c l 80 pf; 10 % to 90 %; 0 v to v cc -- 0.1 s r pu pull-up resistance connected to v cc 79 11 k i pu pull-up current v oh =0.9v cc ; c = 80 pf ? 8 ? 6 ? 4ma data lines to the system: pins i/ouc, aux1uc and aux2uc [4] v ol low-level output voltage i ol =1ma 0 - 0.3 v v oh high-level output voltage no dc load 0.9v dd(intf) -v dd(intf) + 0.1 v i oh 40 a; v dd(intf) >2v 0.75v dd(intf) -v dd(intf) + 0.1 v i oh 20 a; v dd(intf) <2v 0.75v dd(intf) -v dd(intf) +0.1 v v il low-level input voltage ? 0.3 - +0.3v dd(intf) v v ih high-level input voltage 0.7v dd(intf) -v dd(intf) +0.3 v v hys hysteresis voltage pin i/ouc - 0.14v dd(intf) -v i ih high-level input current v ih =v dd(intf) -- 10 a table 7. characteristics of ic supply voltage ?continued v ddp = 5 v; v dd = 3.3 v; v dd(intf) = 3.3 v; f xtal = 10 mhz; gnd = 0 v; t amb = 25 c; unless otherwise specified. symbol parameter conditions min typ max unit tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 17 of 30 nxp semiconductors tda8034hn smart card interface i il low-level input current v il =0v - - 600 a r pu pull-up resistance connected to v dd(intf) 81012 k t r(i) input rise time v il maximum to v ih minimum -- 1.2 s t r(o) output rise time c l 30 pf; 10 % to 90 %; 0 v to v dd(intf) -- 0.1 s t f(i) input fall time v il maximum to v ih minimum -- 1.2 s t f(o) output fall time c l 30 pf; 10 % to 90 %; 0 v to v dd(intf) -- 0.1 s i pu pull-up current v oh =0.9v dd ; c = 30 pf ? 1- - ma internal oscillator f osc(int) internal oscillator frequency shutdown mode 100 150 200 khz active state 2 2.7 3.2 mhz reset output to the card: pin rst v o output voltage shutdown mode no load 0 - 0.1 v i o =1ma 0 - 0.3 v i o output current shutdown mode; pin rst grounded -- ? 1ma t d delay time between pins rstin and rst; rst enabled -- 2 s v ol low-level output voltage i ol = 200 a; v cc = 5 v 0 - 0.3 v i ol = 200 a; v cc = 3 v or 1.8 v 0- 0.2v current limit i ol =20 ma v cc ? 0.4 - v cc v v oh high-level output voltage i oh = ? 200 a0.9v cc -v cc v current limit i oh = ? 20 ma 0 - 0.4 v t r rise time c l = 100 pf - - 0.1 s t f fall time c l = 100 pf - - 0.1 s clock output to the card: pin clk v o output voltage shutdown mode no load 0 - 0.1 v i o =1ma 0 - 0.3 v i o output current shutdown mode; pin clk grounded -- ? 1ma v ol low-level output voltage i ol = 200 a0-0.3v current limit i ol =70ma v cc ? 0.4 - v cc v v oh high-level output voltage i oh = ? 200 a0.9v cc -v cc v current limit i oh = ? 70 ma 0 - 0.4 v t r rise time c l =30pf [5] - - 16 ns t f fall time c l =30pf [5] - - 16 ns table 7. characteristics of ic supply voltage ?continued v ddp = 5 v; v dd = 3.3 v; v dd(intf) = 3.3 v; f xtal = 10 mhz; gnd = 0 v; t amb = 25 c; unless otherwise specified. symbol parameter conditions min typ max unit tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 18 of 30 nxp semiconductors tda8034hn smart card interface f clk frequency on pin clk operational 0 - 20 mhz duty cycle c l =30pf [5] 45 - 55 % sr slew rate rise and fall; c l =30pf v cc =5v 0.2 - - v/ns v cc = 3 v or 1.8 v 0.12 - - v/ns control inputs: pins clkdiv1, clkdi v2, rstin, vcc_sel1 and vcc_sel2 [6] v il low-level input voltage ? 0.3 - 0.3v dd(intf) v v ih high-level input voltage 0.7 v dd(intf) -v dd(intf) +0.3 v v hys hysteresis voltage control input - 0.14v dd(intf) -v i il low-level input current v il =0v - - 1 a i ih high-level input current v ih =v dd(intf) -- 1 a control input: pin cmdvccn [6] v il low-level input voltage ? 0.3 - 0.3v dd(intf) v v ih high-level input voltage 0.7v dd(intf) -v dd(intf) +0.3 v v hys hysteresis voltage control input - 0.14v dd(intf) -v i il low-level input current v il =0v - - 1 a i ih high-level input current v ih =v dd(intf) -- 1 a f cmdvccn frequency on pin cmdvccn -- 100hz t w pulse width 5 v card 30 - - ms 3v card - - 15 ms card detection input: pin presn [6] [7] v il low-level input voltage ? 0.3 - 0.3v dd(intf) v v ih high-level input voltage 0.7v dd(intf) -v dd(intf) + 0.3 v v hys hysteresis voltage pin presn - 0.14v dd(intf) -v i il low-level input current 0 v < v il tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 20 of 30 nxp semiconductors tda8034hn smart card interface 12. application information fig 12. application diagram 001aal142 100 nf c1 v dd(intf) v dd(intf) microcontroller poradj xtal2 18 1 v dd xtal1 aux2uc 17 2 v ddp v dd(intf) 16 3 v cc vcc_sel2 15 14 13 4 rst rstin 5 clk vcc_sel1 6 7 gnd 8 9 10 11 12 24 23 22 21 20 19 tda8034hn 100 nf c2 c3 100 nf c4 10 f r4 0 r1 r2 v dd v dd c5 470 nf c6 220 nf v ddp cmdvccn clkdiv1 aux1uc i/ouc offn clkdiv2 presn i/o aux1 aux2 gnd c5 card connector c1 c6 c2 c7 c3 c8 c4 tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 21 of 30 nxp semiconductors tda8034hn smart card interface 13. package outline fig 13. package outline sot616-1 (hvqfn24) 0.5 1 0.2 a 1 e h b unit y e references outline version european projection issue date iec jedec jeita mm 4.1 3.9 d h 2.25 1.95 y 1 4.1 3.9 2.25 1.95 e 1 2.5 e 2 2.5 0.30 0.18 c 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot616-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot616 -1 h vqfn24: plastic thermal enhanced very thin quad flat package; no leads; 2 4 terminals; body 4 x 4 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 712 24 19 18 13 6 1 x d e c b a e 2 01-08-08 02-10-22 terminal 1 index area terminal 1 index area a c c b v m w m 1/2 e 1/2 e e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 22 of 30 nxp semiconductors tda8034hn smart card interface 14. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 14.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 14.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 23 of 30 nxp semiconductors tda8034hn smart card interface 14.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 14 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 0 and 11 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 14 . table 10. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 11. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 24 of 30 nxp semiconductors tda8034hn smart card interface for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 15. abbreviations msl: moisture sensitivity level fig 14. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 12. abbreviations acronym description emv europay mastercard visa esd electrostatic discharge esr equivalent series resistor fcdm field charged device model hbm human body model ldo low drop-out mm machine model nmos negative-channel metal-oxide semiconductor por power-on reset tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 25 of 30 nxp semiconductors tda8034hn smart card interface 16. revision history table 13. revision history document id release date data sheet status change notice supersedes tda8034hn v.2.0 20101112 product data sheet - tda8034hn_1 modifications: ? table 3 ? pin description ? : table note [4] v dd changed into v dd(intf) table note [5] added iouc, aux1uc, aux2uc re ferenced to new note [5] tda8034hn_1 20100205 product data sheet - - tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 26 of 30 nxp semiconductors tda8034hn smart card interface 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification. tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 27 of 30 nxp semiconductors tda8034hn smart card interface quick reference data ? the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not comple te, exhaustive or legally binding. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 28 of 30 nxp semiconductors tda8034hn smart card interface 19. tables table 1. quick reference data . . . . . . . . . . . . . . . . . . . . .2 table 2. ordering information . . . . . . . . . . . . . . . . . . . . .3 table 3. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 table 4. clock configuration . . . . . . . . . . . . . . . . . . . . . .7 table 5. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .13 table 6. thermal characteristics . . . . . . . . . . . . . . . . . .14 table 7. characteristics of ic supply voltage . . . . . . . .14 table 8. protection characteristics . . . . . . . . . . . . . . . .19 table 9. timing characteristics . . . . . . . . . . . . . . . . . . .19 table 10. snpb eutectic process (from j-std-020c) . . .23 table 11. lead-free process (from j-std-020c) . . . . . .23 table 12. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 13. revision history . . . . . . . . . . . . . . . . . . . . . . . .25 tda8034hn all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2.0. ? 12 november 2010 29 of 30 nxp semiconductors tda8034hn smart card interface 20. figures fig 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 fig 2. pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .4 fig 3. voltage supervisor circuit . . . . . . . . . . . . . . . . . . . .6 fig 4. voltage supervisor waveforms . . . . . . . . . . . . . . . .6 fig 5. basic layout for using an external clock. . . . . . . . .7 fig 6. shutdown and deep shutdown mode activation/deactivation . . . . . . . . . . . . . . . . . . . . . .9 fig 7. activation sequence at t3. . . . . . . . . . . . . . . . . . .10 fig 8. deactivation sequence . . . . . . . . . . . . . . . . . . . . 11 fig 9. emergency deactivation sequence after card removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 fig 10. operation of debounce feature with pins offn, cmdvccn, presn and v cc . . . . . . . . . . . . . . .13 fig 11. definition of output and input transition times . . .19 fig 12. application diagram . . . . . . . . . . . . . . . . . . . . . . .20 fig 13. package outline sot616-1 (hvqfn24) . . . . . . .21 fig 14. temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 nxp semiconductors tda8034hn smart card interface ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 12 november 2010 document identifier: tda8034hn please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 functional description . . . . . . . . . . . . . . . . . . . 5 8.1 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.2 voltage supervisor . . . . . . . . . . . . . . . . . . . . . . 6 8.3 clock circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.4 input and output circuits . . . . . . . . . . . . . . . . . . 8 8.5 shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . 8 8.6 deep shutdown mode. . . . . . . . . . . . . . . . . . . . 8 8.7 activation sequence . . . . . . . . . . . . . . . . . . . . . 9 8.8 deactivation sequence . . . . . . . . . . . . . . . . . . 10 8.9 v cc regulator . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.10 fault detection . . . . . . . . . . . . . . . . . . . . . . . . 11 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 10 thermal characteristics . . . . . . . . . . . . . . . . . 14 11 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 12 application information. . . . . . . . . . . . . . . . . . 20 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 21 14 soldering of smd packages . . . . . . . . . . . . . . 22 14.1 introduction to soldering . . . . . . . . . . . . . . . . . 22 14.2 wave and reflow soldering . . . . . . . . . . . . . . . 22 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22 14.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 25 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 26 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 26 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 17.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 18 contact information. . . . . . . . . . . . . . . . . . . . . 27 19 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 20 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 21 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 |
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